1. Field of the Invention
The present invention relates to a driving apparatus of a plasma display panel (PDP).
2. Description of the Related Art
Various flat panel displays such as the LCD (liquid crystal display), the FED (field emission display), and the plasma display panel (PDP) have been developed. The plasma display panel has a higher resolution, a higher rate of emission efficiency, and a wider view angle in comparison with other flat panel displays. Accordingly, the plasma display panel is viewed as a display that can be substituted for the conventional cathode ray tube (CRT), especially in large-sized displays of greater than forty inches.
The plasma display panel is a flat panel display for showing characters or images using a plasma generated by gas discharge, and includes hundreds of thousands to millions of pixels arranged in a matrix format, in which the number of pixels are determined by the size of the plasma display panel. The plasma display panel is divided into a DC (direct current) plasma display panel and an AC (alternating current) plasma display panel according to applied driving voltage waveforms and structures of discharge cells.
Electrodes of the DC plasma display panel are exposed in a discharge space and the current flows in the discharge space when a voltage is applied, and therefore it is problematic to provide a resistor for current limitation. On the other hand, electrodes of the AC PCP are covered with a dielectric layer, so that currents are limited because of the natural formation of capacitance components, and the electrodes are protected from ion impulses in the case of discharging, and therefore a life span of the AC plasma display panel is longer than that of the DC plasma display panel.
FIG. 1 shows a partial perspective view of a prior art AC plasma display panel. As shown in FIG. 1, scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on a first glass substrate 1, and are covered with a dielectric layer 2 and a protection film 3. A plurality of address electrodes 8 is established on a second glass substrate 6, and the address electrodes 8 are covered with an insulator layer 7. Barrier ribs 9 are formed in parallel with the address electrode 8 on the insulator layer 7 between the address electrodes 8, and phosphors 10 are formed on the surface of the insulator layer 7 and on the both sides of the barrier ribs 9. The first and second glass substrates 1 and 6 are provided to face with each other with a discharge spaces 11 between the glass substrates 1 and 6 so that the scan electrodes 4 and the sustain electrodes 5 may respectively cross the address electrodes 8. A discharge space 11 between the address electrode 8 and a crossing part of a pair of the scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.
FIG. 2 schematically shows an electrode arrangement of a prior art plasma display panel. As shown in FIG. 2, the electrodes of the plasma display panel comprise an M×N matrix format. The address electrodes A1 to Am are arranged in the column direction, and N scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are alternately arranged in the row direction. The scan electrode will be referred to as “Y electrodes”and the sustain electrodes referred to as “X electrodes. ” The discharge cell 12 in FIG. 2 corresponds to the discharge cell 12 in FIG. 1.
FIG. 3 shows a diagram of a driving waveform associated with a conventional plasma display panel. According to the plasma display panel driving method shown in FIG. 3, each subfield includes a reset period, an address period, and a sustain period. In the reset period, wall charges of previous sustain-discharging are erased, and the wall charges are generated so as to perform the next address discharging stably. In the address period, cells that are turned on and those that are turned off on the panel are selected, and the wall charges are accumulated to the cells that are turned on (i.e., addressed cells). In the sustain period, discharge for substantially displaying images on the addressed cells is performed.
An operation of the plasma display panel driving method in the reset period will be described. As shown in FIG. 3, the reset period comprises a Y ramp rising period and a Y ramp falling period.
(1) Y ramp rising period
A ramp reset waveform gradually rising from a voltage of VS to a voltage of Vset is applied to the Y electrode while the address electrode and the X electrode are maintained at 0V in the period. A first weak reset discharging is generated to the address electrode and the X electrode from the Y electrode in the discharge cells while the ramp reset waveform is rising. Accordingly, (−) wall charges are accumulated on the Y electrode, and (+) charges are concurrently accumulated on the address electrode and the X electrode.
(2) Y ramp falling period
A ramp reset waveform gradually falling from a voltage of VS to a negative voltage of Vnf is applied to the Y electrode while the X electrode is maintained at a constant voltage of Ve. A second weak reset discharging is generated in the discharge cells while the ramp reset waveform is falling.
FIG. 4 shows a diagram of a conventional plasma display panel driving circuit for realizing the driving waveforms shown in FIG. 3. According to the conventional driving circuit shown in FIG. 4, a main switch Ypp is necessary for separating a voltage applied in the Y ramp rising period (a period in which a voltage applied to a panel capacitor rises to the voltage of Vset from the voltage of VS when a switch Yπ is turned on) from the voltage of VS. A plurality of field effect transistors (FETs) coupled in parallel are substantially necessary because the main switch Ypp is provided on a main discharge path. Therefore it is problematic that a size of entire board and a cost are increased because impedance and the number of parts of a circuit are increased according the conventional driving circuit. It is also problematic that increased impedance on the main path according to the conventional driving circuit has an effect on a discharge margin in the case of the sustain discharging.